This invention relates generally to transformers formed on an integrated circuit substrate, and more specifically to transformers having an outer core spanning at least three metal layers of the integrated circuit substrate.
The current revolution in wireless communications and the need for smaller wireless communications devices has spawned significant efforts directed to the optimization and miniaturization of radio communications electronics devices. Passive components of these devices (such as inductors, capacitors and transformers), play a necessary role in the devices"" operation and thus efforts are directed toward reducing the size and improving the fabrication efficiency of such components.
Transformers, which play an integral role in the performance of electronic communications devices, are electromagnetic components comprising a primary and a secondary winding. Conventionally, the windings are wound on a common core, which forms a closed loop magnetic circuit. Iron cores are typical to enhance the transformer effect, but not required. Each winding comprises a plurality of turns. The relationship between the primary and secondary voltage is a function of the primary to secondary turns ratio, and the relationship between the primary and secondary current is an inverse function of the turns ratio. As is known, there are many different physical configurations for the transformer windings and core. In one embodiment, for example, the primary and secondary windings form a helical structure, with the secondary windings oriented within the opening formed by the primary windings. Transformers also serve in varied applications, including power applications for stepping applied voltages up or down and for impedance matching at frequencies from audio to radio frequency (RF). With the continual allocation of operational communications frequencies into higher frequency bands, transformers used in impedance-matching applications suffer impaired performance due to increased eddy current and skin effect losses.
The Q (or quality factor) is an important transformer figure of merit. The Q measures the ratio of inductive reactance to inductive resistance within the transformer windings. High Q transformers present a narrow peak when the transformer current is graphed as a function of the input signal frequency, with the peak representing the frequency at which the transformer resonates. High Q transformers are especially important for use in frequency-dependent circuits operating with narrow bandwidths. Because the Q value is an inverse function of transformer resistance, it is especially important to minimize the resistance to increase the Q.
Most personal communications devices incorporate integrated circuit active components fabricated using semiconductor technologies, such as silicon or gallium-arsenide. The prior art teaches certain integrated inductive structures (including torroidal or spiral shaped inductors) developed to achieve compatibility with the silicon-based integrated circuit fabrication processes. When two such inductors are proximately formed, the coupling of the magnetic field formed by current flow through one winding (the primary) into the winding area of the other winding (the secondary) results in transformer action and the flow of current in the secondary. However, such planar inductors tend to suffer from high losses and low Q factors at the operative frequencies of interest. These losses and low Q factors are generally attributable to dielectric losses caused by parasitic capacitances and resistive losses due to the use of thin and relatively high resistivity conductors in the transformer structure. Another disadvantage of conventional planar inductors and transformers formed from them is a result of the magnetic field lines (which are perpendicular to the semiconductor substrate surface) entering the semiconductor and dielectric layers above, beside and below the transformer. This increases the inductive losses and lowers the transformer""s Q factor. Also, unless the transformer is located a significant distance from active circuit elements formed in the silicon, the magnetic field lines induce currents in and therefore disrupt operation of the active components.
With integrated circuit active devices growing smaller and operating at higher speeds, the interconnect system should not add processing delays to the device signals. Use of conventional aluminum interconnect metallization restricts circuit operational speed as the longer interconnects and smaller interconnect cross-sections increase the interconnect resistance. Also, the relatively small contact resistance between the aluminum and silicon surfaces creates a significant total resistance as the number of circuit components grows. It is also difficult to deposit aluminum with a high aspect ratio in vias and plugs, where the aspect ratio is defined as the ratio of plug thickness to diameter.
Given theses disadvantages, copper is becoming the interconnect of choice because it is a better conductor than aluminum (with a resistance of 1.7 micro-ohm cm compared to 3.1 micro-ohm cm for aluminum), is less susceptible to electromigration, can be deposited at lower temperatures (thereby avoiding deleterious effects on the device dopant profiles) and is suitable for use as a plug material in a high aspect ration plug. Copper interconnects can be formed by chemical vapor deposition, sputtering, electroplating and electrolytic plating.
The damascene process is one technique for forming active device copper interconnects. A trench is formed in a surface dielectric layer and the copper material is then deposited therein. Usually the trench is overfilled, requiring a chemical and mechanical polishing step to re-planarize the surface. This process offers superior dimensional control because it eliminates the dimensional variations introduced in a typical pattern and etch interconnect process. The dual damascene process extends the damascene process, simultaneously forming both the underlying conductive vias and the interconnecting trenches from copper. First the via opening is formed, followed by formation of a trench between two via openings to be interconnected. A subsequent metal deposition step fills both the via openings and the trench, forming an integral metal layer and conductive via to the metal layer below. A chemical and mechanical polishing step planarizes the top surface or the substrate. Dual damascene processes are discussed in detail in the following references, which are hereby incorporated by reference: C. K. Hu et. al., Proceedings MRS Symposium on VLSI, vol. 5, p. 369 (1990); B. Luther et. al. Proceedings VMIC, vol. 10, p. 15 (1994); D. Edelstein, Proceedings ECS Mtg., vol. 96-2, p. 335 (1996).
To provide further advances in the fabrication of transformers in conjunction with active devices on a semiconductor substrate, an architecture and processes is provided for forming such a transformer within the conventional metal layers of an integrated circuit, wherein the transformer core area is larger than prior art transformers, resulting in a higher inductance value and a higher Q figure of merit. Also, a transformer formed according to the teachings of the present inventions has a desirable low-resistance (and thus high Q) in a relatively compact area of the integrated circuit.
According to one embodiment of the invention, a plurality of parallel lower conductive strips are formed overlying the semiconductor substrate, in which active components were previously formed. First and second vertical conductive via openings are formed over first and second opposing edges of each lower conductive strip and conductive material is deposited within the via openings to form first and second conductive vias. Two additional via openings are formed in vertical alignment with the first and the second conductive vias and filled with metal to form third and fourth conductive vias. A plurality of upper conductive strips are then formed, wherein the plane of an upper conductive strip intersects the plane of a lower conductive strip such that a first edge of one upper conductive strip overlies the first edge of a lower conductive strip, and the two edges are interconnected by the first and the third conductive vias. A second edge of the upper conductive strip overlies the second edge of the next parallel lower conductive strip, and these edges are electrically connected by the second and the fourth conductive vias. Thus is formed an outer helical winding of the transformer. An inner winding of the transformer is similarly formed. The bottom segment of the inner winding is formed at least one metal layer above the bottom segment of the outer winding, and the top segment of the inner winding is at least one metal layer below the top segment of the inner winding. Although the transformer must be formed in at least four metal layers (i.e., the bottom segment of the inner and windings and the top segment of the inner and outer windings), there can be more than one metal layer between the various winding segments and the bottom segment of the outer winding can be formed on any of the integrated circuit metal layers, with the additional winding segments formed above it.
The use of certain layout and metallization techniques for constructing a transformer according to the techniques of the present invention result in lower resistive losses in the conductive material, thereby reducing eddy current losses and also increasing the transformer Q factor. According to one embodiment of the present invention, a multi-layer dual-damascene metallization techniques is employed to form the transformer. A plurality of parallel metal-1 runners are formed in a first stack of insulating materials. A second stack of insulating materials is disposed over the first stack and a plurality of first and second via openings are formed therein, wherein each one of the plurality of first via openings is in contact with a first end of a metal-1 runner, and each one of the plurality of second via openings is in contact with a second end of the metal-1 runner. A metal-2 trench is formed within one or more upper layers of the second stack, and the first and the second via openings and trench are then filled with copper. The metal-2 runner is set back from the vertical plane of the metal-1 runner. A third stack of insulating layers is disposed over the second stack and four via openings are formed therein. Third and fourth via openings are each in electrical contact with one of the first and second conductive vias, respectively. Fifth via openings are in contact with a first end of the metal-2 trench and sixth via openings are in contact with a second end of the metal-2 trench. A metal-3 trench is formed interconnecting the upper end of the fifth and sixth via openings, but the metal-3 trench connects two successive metal-2 runners. Thus one end of the metal-3 trench is connected to a sixth via opening of a metal-2 runner and the other end of the metal-3 trench connects with the fifth via opening of the next metal-2 runner in the plurality of parallel metal-2 runners. The third, fourth, fifth and sixth via openings and the metal-3 trenches are then filled with copper. A fourth stack of insulating layers is disposed over the structure and seventh and eighth via openings are formed therein and vertically aligned with the third and fourth conductive vias, respectively. A metal-4 trench is formed in the upper portion of the top insulating stack, with one end of the metal-4 runner in contact with an eighth via opening, and the other end of the metal-4 trench in contact with a seventh via opening of the next metal-1 runner in the plurality of parallel metal-1 runners. In this way, the metal-4 trench interconnects two successive metal-1 runners. The metal-4 trench and the seventh and eighth via openings are filled with copper. In a cross sectional view, the resulting structure forms two concentric rectangles of conductive material. In the top view, the metal-1 and metal-4 runners form a helix with each metal-4 runner interconnecting successive metal-1 runners. Similarly, the metal-2 and metal-3 runners form a helix with each metal-3 runner electrically interconnecting successive metal-2 runners. The resulting structure comprises a transformer, with an outer winding formed by the metal-1 and metal-4 runners and an inner winding formed by the metal-2 and metal-3 runners.